A stacked carbon nanotube (CNT) memory cube array can be a three dimensional (3-D) version of a nanotube random access memory (NRAM) array, where CNT memory arrays are stacked vertically (e.g., along the z-axis). A conventional method of selecting a CNT memory cell in a two dimensional (2-D) CNT memory array (e.g., in the plane of the substrate, i.e., x-y plane) is to use a transistor switch coupled to each CNT memory cell. When the transistor switch is in a low resistance state (e.g., ON state) the CNT memory cell becomes active and can toggle between logic low and high states. One problem with the transistor switching is that the density of the memory cells is limited by the density of the underlying transistors.
Improvements in density can be obtained if diodes are employed to select the memory cells instead of transistors. Replacing transistors with diodes provides a potential for CNT memory cell sizes of the order of less than 10 f2, where f represents a lowest feature size (e.g., 45 nm) of the applied fabrication technology. Despite the potential density improvements resulting from using diodes to replace switch transistors and/or employing some photolithography tricks (which are not necessarily transferable to real integration), the density of the CNT memory devices are still heavily limited by the 2-D structure of the CNT memory devices and the underlying addressing circuitry. Therefore, high density CNT memory devices are desirable.